The present disclosure generally relates to semiconductor structures, and more particularly to bulk fin field effect transistor (FinFET) devices including self-aligned isolation regions with varying depth, and a method for making the same.
Complementary metal-oxide-semiconductor (CMOS) technology is commonly used for fabricating field effect transistors (FETs) as part of advanced integrated circuits (IC), such as CPUs, memory, storage devices, and the like. As integrated circuits continue to scale downward in size, there is a growing need in CMOS technology to achieve higher device density without affecting performance and/or reliability while keeping production costs down.
With the aim of increasing device density, fin field effect transistors (FinFETs) or tri-gate structures are becoming more widely used, primarily because FinFETs offer better performance than planar FETs at the same power budget. FinFETs are three dimensional (3-D), fully depleted metal-oxide semiconductor field effect transistor (MOSFET) devices representing an important part of CMOS fabrication technology to create microelectronic devices with ever-decreasing dimensions.
FinFETs have a fin structure formed from a semiconductor substrate material. The fin forms a channel region located between a source region and a drain region. A gate structure is located over the fin enfolding the channel region. Such architecture allows for a more precise control of the conducting channel by the gate, significantly reducing the amount of current leakage when the device is in off state.
In order to keep each FinFET device electrically isolated from one another, FinFETs are generally fabricated from silicon-on-insulator (SOI) substrates. The source and drain of adjacent FinFET devices are isolated from one another in order to provide source to drain decoupling. However, the high cost of SOI substrates may potentially affect the scalability of CMOS FinFET manufacturing. Bulk silicon wafers, or bulk substrates, may offer a more cost-effective alternative to SOI substrates in FinFET manufacturing.
In bulk FinFET technology, isolation regions may be used to electrically insulate adjacent devices or to electrically separate the fins of a given device from one another. Typically, isolation regions may include at least two different depths within the bulk substrate. One shallow isolation region separating fins that belong to an individual device having a shared source and drain region, and a deeper isolation region that separates adjacent source and drain regions of different devices. Currently, this may be achieved by using two different masks, one that defines the fins and one that defines the deeper isolation region. In such an instance, the process may be prone to misalignment of lithography masks.
Typically, an upper surface of one isolation region, for example, a shallow isolation region may be substantially flush with an upper surface of another isolation region, for example, a deep isolation region. This may hinder several processing steps, such as, for example chemical mechanical polish of gate structures and epi isolation.